The present invention relates generally to integrated circuit memory devices, and, more particularly, to an apparatus and method for improved SRAM device performance through use of a double gate topology.
A typical static random access memory (SRAM) includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value therein, which voltage value represents a logical data bit (e.g., “0” or “1”). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. With CMOS (complementary metal oxide semiconductor) technology, the inverters further include a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor. The inverters, connected in a cross-coupled configuration, act as a latch that stores the data bit therein so long as power is supplied to the memory array. In a conventional six-transistor cell, a pair of access transistors or pass gates (when activated by a word line) selectively couples the inverters to a pair of complementary bit lines.
The design of SRAM cells has traditionally involved a compromise between the read and write functions of the memory cell to maintain cell stability, read performance and write performance. The transistors which make up the cross couple must be weak enough to be overdriven during a write operation, while strong enough to maintain their data value when driving a bitline during a read operation. The transfer gates that connect the cross coupled nodes to the true and compliment bitlines affect both the stability and performance of the cell. In one-port SRAM cells, a single pair of transfer gates is conventionally used for both read and write access to the cell. These gates are driven to a digital value to switch the transfer gates between an on and off state.
The optimization of a transfer gate for a write operation would drive the reduction of the on-resistance (Ron) for the device. On the other hand, the optimization of a transfer gate for a read operation drives an increase in Ron in order to isolate the cell from the bitline capacitance and prevent a cell disturb.
Accordingly, it would be desirable to be able to optimize the read and write performance of an SRAM device notwithstanding the inherent tradeoff aspects described above, and in a manner that reduces device area while still maintaining cell stability.